Thin film transistor array panel

ABSTRACT

A thin film transistor array panel according to an embodiment of the present invention includes: a gate electrode; a semiconductor layer; a gate insulating layer disposed between the gate electrode and the semiconductor layer; a source electrode connected to the semiconductor layer; and a drain electrode connected to the semiconductor layer, spaced apart from the source electrode, and including two branches overlapping the gate electrode, wherein the two branches of the drain electrode are spaced apart from each other and lie on a straight line or on two parallel straight lines.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority from Korean Patent Application No.10-2004-0088812 filed on Nov. 3, 2004, the disclosure of which isincorporated herein by reference in its entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a thin film transistor array panel.

2. Description of Related Art

An active type display device such as a liquid crystal display (LCD) andan organic light emitting diode (OLED) display includes a plurality ofpixels arranged in a matrix and including field generating electrodesand switching elements. The switching elements include thin filmtransistors (TFTs) having three terminals, gate, source, and drain. TheTFT of each pixel selectively transmits data signals to afield-generating electrode in response to gate signals.

The display device further includes a plurality of signal lines fortransmitting signals to the switching elements, which includes gatelines transmitting gate signals and data lines transmitting datasignals.

The LCD and the OLED include a panel provided with TFTs,field-generating electrodes, and signal lines, which is referred to as aTFT array panel.

The TFT array panel has a layered structure that includes severalconductive layers and insulating layers. Gate lines, data lines, andfield-generating electrodes are formed of different conductive layersand separated by insulating layers.

When an active area on a backplane for LCDs is too large to use anexposure mask, the entire exposure is accomplished by repeating adivisional exposure called step-and-repeat process. One divisionalexposure unit or area is called a shot. Since transition, rotation, anddistortion are generated during light exposure, the shots are notaligned accurately. Accordingly, parasitic capacitances generatedbetween signal lines and pixel electrodes differ depending on the shots,and this causes the luminance difference between the shots, which isrecognized at the pixels located at a boundary between the shots.Therefore, the stitch defect is generated on the screen of the LCD dueto luminance discontinuity between the shots. In addition, thedifference in the parasitic capacitance causes the difference in thekickback voltage to yield flickering.

SUMMARY OF THE INVENTION

A thin film transistor array panel according to an embodiment of thepresent invention includes: a gate electrode; a semiconductor layer; agate insulating layer disposed between the gate electrode and thesemiconductor layer; a source electrode connected to the semiconductorlayer; and a drain electrode connected to the semiconductor layer,spaced apart from the source electrode, and including two branchesoverlapping the gate electrode, wherein the two branches of the drainelectrode are spaced apart from each other and lie on a straight line oron two parallel straight lines.

The gate electrode may have two opposite edges meeting the two branches,respectively, and substantially parallel to each other.

The thin film transistor array panel may further include: a gate linecoupled to the gate electrode; a data line coupled to the drainelectrode; and a pixel electrode coupled to the drain electrode.

The two branches may have a symmetry with respect to a center linepassing through the gate electrode and parallel to the gate line or thedata line.

The source electrode may enclose the two branches.

The source electrode may have a symmetry with respect to the center linepassing through the gate electrode and parallel to the gate line or thedata line.

The source electrode may be spaced apart from the gate line except forthe source electrode.

The source electrode may have a shape of a character H or a shape of acharacter H rotated by about a right angle.

The pixel electrode may include a lower half and an upper half that aredisposed opposite each other with respect to the gate line.

The drain electrode may have a symmetry with respect to a center line ofthe gate line.

The thin film transistor array panel may further include a storageelectrode line overlapping at least one of the pixel electrode and thedrain electrode.

The storage electrode may be disposed near an edge of the pixelelectrode.

The storage electrode may be disposed near an edge of the pixelelectrode.

A thin film transistor according to another embodiment includes: a gateelectrode having a first edge and a second edge disposed opposite thefirst edge; a semiconductor layer; a gate insulating layer disposedbetween the gate electrode and the semiconductor layer; a sourceelectrode connected to the semiconductor layer; a drain electrodeconnected to the semiconductor layer, spaced apart from the sourceelectrode, and including a first branch and a second branch, wherein thefirst branch meets the first edge of the gate electrode at apredetermined angle, the second branch meets the second edge of the gateelectrode at the predetermined angle.

The first edge of the gate electrode may be substantially parallel tothe second edge of the gate electrode.

A thin film transistor array panel according to another embodimentincludes: a gate line including a gate electrode; a data lineintersecting the gate line and including a source electrode; a drainelectrode disposed apart from the source electrode and including twobranches; a semiconductor layer connected to the source electrode andthe drain electrode; a passivation layer formed on the gate line, thedata line, the drain electrode, and the semiconductor layer; and a pixelelectrode connected to the drain electrode, wherein the source electrodeincludes two concave portions connected to each other and disposedopposite each other and the two concave portions enclose respectivebranches of the drain electrode.

The source electrode may include a connecting portion connected betweenthe concave portions and the data line and the connecting portion may bespaced apart from the gate line.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will become more apparent by describingembodiments thereof in detail with reference to the accompanying drawingin which:

FIG. 1 shows a layout view of a TFT array panel according to anembodiment of the present invention;

FIG. 2 shows a sectional view of the TFT array panel shown in FIG. 1taken along the line II-II′;

FIG. 3 shows a layout view of a TFT array panel for an LCD according toanother embodiment of the present invention;

FIG. 4 shows a sectional view of the TFT array panel shown in FIG. 3taken along the line IV-IV′;

FIG. 5 shows a sectional view of the TFT array panel shown in FIG. 3taken along the line V-V′;

FIG. 6 shows a layout view of a TFT array panel for an LCD according toanother embodiment of the present invention;

FIG. 7 shows a layout view of a common electrode panel for an LCDaccording to an embodiment of the present invention;

FIG. 8 shows a sectional view of an LCD including the TFT array panelshown in FIG. 6 and the common electrode panel shown in FIG. 7;

FIG. 9 shows a sectional view of the LCD shown in FIG. 8 taken along theline IX-IX′;

FIG. 10 shows a layout view of a TFT array panel for an LCD according toanother embodiment of the present invention;

FIG. 11 shows a layout view of a common electrode panel for an LCDaccording to another embodiment of the present invention;

FIG. 12 shows a sectional view of an LCD including the TFT array panelshown in FIG. 10 and the common electrode panel shown in FIG. 11;

FIG. 13 shows a sectional view of the LCD shown in FIG. 12 taken alongthe line XIII-XIII′;

FIG. 14 shows a layout view of an LCD according to another embodiment ofthe present invention;

FIG. 15 shows a sectional view of the LCD shown in FIG. 12 taken alongthe line XV-XV′; and

FIG. 16 shows a layout view of an LCD according to another embodiment ofthe present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

The present invention now will be described more fully hereinafter withreference to the accompanying drawings, in which preferred embodimentsof the invention are shown. This invention may, however, be embodied inmany different forms and should not be construed as limited to theembodiments set forth herein.

In the drawings, the thickness of layers and regions are exaggerated forclarity. Like numerals refer to like elements throughout. It will beunderstood that when an element such as a layer, region or substrate isreferred to as being “on” another element, it can be directly on theother element or intervening elements may also be present. In contrast,when an element is referred to as being “directly on” another element,there are no intervening elements present.

A TFT array panel according to an embodiment of the present inventionwill be described in detail with reference to FIGS. 1 and 2.

FIG. 1 shows a layout view of a TFT array panel according to anembodiment of the present invention, and FIG. 2 shows a sectional viewof the TFT array panel shown in FIG. 1 taken along the line II-II′.

A plurality of gate lines 121 is formed on an insulating substrate 110such as transparent glass or plastic.

The gate lines 121 transmit gate signals and extend substantially in atransverse direction. Each of the gate lines 121 includes a plurality ofgate electrodes 124 projecting upwardly, a plurality of gate lineprojections 127 projecting downwardly, and a gate line end portion 129having a large area for contact with another layer (not shown) or anexternal driving circuit (not shown). A gate driving circuit (not shown)for generating gate signals may be mounted on a flexible printed circuit(FPC) film (not shown), which may be attached to the insulatingsubstrate 110, directly mounted on the insulating substrate 110, orintegrated onto the insulating substrate 110. The gate lines 121 mayextend to be connected to a driving circuit (not shown) that may beintegrated on the insulating substrate 110.

The gate lines 121 are preferably made of Al containing metal such as Aland Al alloy, Ag containing metal such as Ag and Ag alloy, Cu containingmetal such as Cu and Cu alloy, Mo containing metal such as Mo and Moalloy, Cr, Ta, or Ti. However, they may have a multi-layered structureincluding two conductive films (not shown) having different physicalcharacteristics. One of the two films is preferably made of lowresistivity metal including Al containing metal, Ag containing metal,and Cu containing metal for reducing signal delay or voltage drop. Theother film is preferably made of material such as Mo containing metal,Cr, Ta, or Ti, which has good physical, chemical, and electrical contactcharacteristics with other materials such as indium tin oxide (ITO) orindium zinc oxide (IZO). Good examples of the combination of the twofilms are a lower Cr film and an upper Al (alloy) film and a lower Al(alloy) film and an upper Mo (alloy) film. However, the gate lines 121may be made of other metals or conductors.

Lateral sides of the gate lines 121 are inclined relative to a surfaceof the insulating substrate 110, and the inclination angle thereofranges about 30-80 degrees.

A gate insulating layer 140 preferably made of silicon nitride (SiNx) orsilicon oxide (SiOx) is formed on the gate lines 121.

A plurality of first and second semiconductor islands 151 and 154preferably made of hydrogenated amorphous silicon (abbreviated to“A-Si”) or polysilicon is formed on the gate insulating layer 140. Thesecond semiconductor islands 154 are disposed on the gate electrodes 124such that edges of the second semiconductor islands 154 are disposed onthe gate electrodes 124 to block a light emitted from a backlight lampfrom being incident onto the second semiconductor islands 154, therebyreducing a photocurrent. The first semiconductor islands 151 aredisposed on the gate lines 121 and cover lower and upper edges of thegate lines 121.

A plurality of second and third ohmic contact islands 163 and 165 areformed on the second semiconductor islands 154. A plurality of firstohmic contacts 161 are also formed on the first semiconductor islands151. The first, second and third ohmic contacts 161, 163 and 165 arepreferably made of n+hydrogenated A-Si heavily doped with n typeimpurity such as phosphorous or they may be made of silicide.

The lateral sides of the first and second semiconductor islands 151 and154 and the first, second and third ohmic contacts 161, 163 and 165 areinclined relative to the surface of the insulating substrate 110, andthe inclination angles thereof are preferably in a range of about 30-80degrees.

A plurality of data lines 171, a plurality of drain electrodes 175, anda plurality of storage capacitor conductors 177 are formed on the first,second and third ohmic contacts 161, 163 and 165 and the gate insulatinglayer 140.

The data lines 171 transmit data signals and extend substantially in alongitudinal direction to intersect the gate lines 121. Each data line171 includes a plurality of source electrodes 173 projecting toward thegate electrodes 124 and having a bilateral symmetry on the gateelectrodes 124. Each of the source electrodes 173 includes alongitudinal portion and two pairs of transverse portions extending fromboth ends of the longitudinal portion in left and right directionshaving a shape like a character “H” rotated about 90 degrees. Each ofthe data lines 171 further includes a data line end portion 179 having alarge area for contact with another layer (not shown) or an externaldriving circuit (not shown). A data driving circuit (not shown) forgenerating the data signals may be mounted on a FPC film (not shown),which may be attached to the insulating substrate 110, directly mountedon the insulating substrate 110, or integrated onto the insulatingsubstrate 110. The data lines 171 may extend to be connected to adriving circuit (not shown) that may be integrated on the insulatingsubstrate 110.

The drain electrodes 175 are separated from the data lines 171 anddisposed opposite the source electrodes 173 with respect to the gateelectrodes 124. Each of the drain electrodes 175 includes a wide portionand two branches. The two branches lie on a straight line or on twoparallel straight lines and are spaced apart from each other. Thebranches form a hook portion having a bilateral symmetry. The hookportion has a shape like a character “C” and is disposed partlyenclosing a gate electrode 124, and end portions of the hook portionpass through opposite longitudinal edges to reach inner portions of thegate electrode 124. Both ends of the hook portion are disposed on a gateelectrode 124 and partly enclosed by a source electrode 173.

The symmetrical arrangement of the drain electrodes 175 with respect tothe gate electrodes 124 causes a uniform overlapping area between thedrain electrodes 175 and the gate electrodes 124 regardless ofdeformation of masks such as transition, rotation, and twist. Althoughmasks for forming the gate electrodes 124 and the drain electrodes 175are shifted, rotated, or twisted to misalign the gate electrodes 124 andthe drain electrodes 175 in a transverse direction such that one of leftand right overlapping areas between the gate electrodes 124 and thedrain electrodes 175 is decreased, the other of the left and rightoverlapping areas is increased to compensate from the decrease of theone overlapping area. Accordingly, the parasitic capacitances betweenthe gate electrodes 124 and the drain electrodes 175 can be maintaineduniformly to reduce the flickering of the image. In addition, thelongitudinal misalignment between the gate electrodes 124 and the drainelectrodes 175 does not affect the overlapping area between the gateelectrodes 124 and the drain electrodes 175.

The storage capacitor conductors 177 overlap the gate line projections127.

A gate electrode 124, a source electrode 173, and a drain electrode 175along with a projection of a second semiconductor island 154 form a TFThaving a channel formed in the second semiconductor island 154 disposedbetween the source electrode 173 and the drain electrode 175.

The data lines 171, the drain electrodes 175, and the storage capacitorconductors 177 are preferably made of a refractory metal such as Cr, Mo,Ta, Ti, or alloys thereof. However, they may have a multilayeredstructure including a refractory metal film (not shown) and a lowresistivity film (not shown). Examples of the multi-layered structureare a double-layered structure including a lower Cr/Mo (alloy) film andan upper Al (alloy) film and a triple-layered structure of a lower Mo(alloy) film, an intermediate Al (alloy) film, and an upper Mo (alloy)film. However, the data lines 171, the drain electrodes 175, and thestorage capacitor conductors 177 may be made of other metals orconductors.

The data lines 171, the drain electrodes 175, and the storage capacitorconductors 177 have inclined edge profiles, and the inclination anglesthereof range about 30-80 degrees.

The first, second and third ohmic contacts 161, 163 and 165 areinterposed only between the underlying first and second semiconductorislands 151 and 154 and the overlying data lines 171 and drainelectrodes 175 thereon and reduce the contact resistance therebetween.The first semiconductor islands 151 smooth the profile of the surface,thereby preventing the disconnection of the data lines 171. The firstand second semiconductor islands 151 and 154 include some exposedportions, which are not covered with the data lines 171, the drainelectrodes 175, or the storage capacitor conductors 177, such asportions located between the source electrodes 173 and the drainelectrodes 175.

A passivation layer 180 is formed on the data lines 171, the drainelectrodes 175, the storage capacitor electrodes 177, and the exposedportions of the first and second semiconductor islands 151 and 154. Thepassivation layer 180 is preferably made of an inorganic or organicinsulator and it may have a flat top surface. Examples of the inorganicinsulator include silicon nitride and silicon oxide. The organicinsulator may have photosensitivity and a dielectric constant of lessthan about 4.0. The passivation layer 180 may include a lower film of aninorganic insulator and an upper film of an organic insulator such thatit takes the excellent insulating characteristics of the organicinsulator while preventing the exposed portions of the first and secondsemiconductor islands 151 and 154 from being damaged by the organicinsulator.

The passivation layer 180 has a plurality of second, third and fourthcontact holes 182, 185 and 187 exposing the data line end portions 179,the drain electrodes 175, and the gate line projections 127,respectively. The passivation layer 180 and the gate insulating layer140 have a plurality of first contact holes 181 exposing the gate lineend portions 129.

A plurality of pixel electrodes 190 and a plurality of first and secondcontact assistants 81 and 82 are formed on the passivation layer 180.They are preferably made of transparent conductor such as ITO or IZO orreflective conductor such as Ag, Al, Cr, or alloys thereof.

The pixel electrodes 190 are physically and electrically connected tothe drain electrodes 175 through the third contact holes 185 such thatthe pixel electrodes 190 receive data voltages from the drain electrodes175. The pixel 10 electrodes 190 supplied with the data voltagesgenerate electric fields in cooperation with a common electrode (notshown) of an opposing display panel (not shown) supplied with a commonvoltage, which determine the orientations of liquid crystal (LC)molecules (not shown) of an LC layer (not shown) disposed between thepixel electrodes 190 and the common electrode. A pixel electrode 190 andthe common electrode form a capacitor referred to as a “liquid crystalcapacitor,” which stores applied voltages after the TFT turns off.

In addition, the pixel electrodes 190 are connected to the storagecapacitor conductors 177 overlapping the gate line projections 127. Apixel electrode 190 and a storage capacitor conductor 177 connectedthereto and a gate line projection 127 form an additional capacitorreferred to as a “storage capacitor,” which enhances the voltage storingcapacity of the liquid crystal capacitor.

A TFT array panel for an LCD according to another embodiment of thepresent invention will be described in detail with reference to FIGS. 3,4 and 5.

FIG. 3 shows a layout view of a TFT array panel for an LCD according toanother embodiment of the present invention, FIG. 4 shows a sectionalview of the TFT array panel shown in FIG. 3 taken along the line IV-IV′,and FIG. 5 shows a sectional view of the TFT array panel shown in FIG. 3taken along the line V-V′.

Referring to FIGS. 3-5, the layered structure of the TFT array panelaccording to this embodiment is similar to those shown in FIGS. 1 and 2.

That is, a plurality of gate lines 121 including gate electrodes 124 areformed on an insulating substrate 110, and a gate insulating layer 140,a plurality of semiconductor stripes 152 including a plurality ofsemiconductor stripe projections 153, and a plurality of ohmic contacts161 including ohmic contact projections 163 and a plurality of ohmiccontact islands 165 are sequentially formed thereon. A plurality of datalines 171 including source electrodes 173, a plurality of drainelectrodes 175, and a plurality of storage capacitor conductors 177 areformed on the ohmic contact stripes and islands 161 and 165, and apassivation layer 180 is formed thereon. A plurality of first, second,third and fourth contact holes 181, 182, 185 and 187 are provided at thepassivation layer 180 and the gate insulating layer 140. A plurality ofpixel electrodes 190 and a plurality of first and second contactassistants 81 and 82 are formed on the passivation layer 180.

In this embodiment, the source electrodes 173 are spaced apart from thegate lines 121.

Furthermore, the TFT array panel according to this embodiment provides aplurality of storage electrode lines 131, which are separated from thegate lines 121, on the same layer as the gate lines 121 without gateline projections. The storage electrode lines 131 are supplied with apredetermined voltage such as the common voltage and extendsubstantially parallel to the gate lines 121. Each of the storageelectrode lines 131 is disposed between two adjacent gate lines 121 andit is nearly equidistant from the two adjacent gate lines 121. Thestorage electrode lines 131 overlap the storage capacitor conductors 177to form storage capacitors.

However, the storage electrode lines 131 may have various shapes andarrangements. For example, the storage electrode lines 131 may beomitted if the storage capacitance generated by the overlap of the gatelines 121 and the pixel electrodes 190 is sufficient. The storageelectrode lines 131 may be disposed near the gate lines 121 to increasethe aperture ratio.

In addition, the semiconductor stripes 152 of the TFT array panel 100according to this embodiment have similar planar shapes as the datalines 171 and the drain electrodes 175 as well as the underlying ohmiccontact stripes and islands 161 and 165. However, the semiconductorstripe projections 153 include some exposed portions, which are notcovered with the data lines 171 or the drain electrodes 175, such asportions located between the source electrodes 173 and the drainelectrodes 175.

Furthermore, the TFT array panel 100 further includes a plurality offifth semiconductor islands 157 and a plurality of fifth ohmic contactislands 167 disposed under the storage capacitor conductors 177.

A manufacturing method of the TFT array panel according to an embodimentsimultaneously forms the data lines 171, the drain electrodes 175, thesemiconductors 151, and the ohmic contact stripes and islands 161 and165 using one photolithography process.

A photoresist pattern for the photolithography process hasposition-dependent thickness, and in particular, it has first and secondportions with decreasing thickness. The first portions are located onwire areas that will be occupied by the data lines 171 and the drainelectrodes 175, and the second portions are located on channel areas ofthe TFTs.

The position-dependent thickness of the photoresist is obtained byseveral techniques, for example, by providing translucent areas on theexposure mask as well as transparent areas and light blocking opaqueareas. The translucent areas may have a slit pattern, a lattice pattern,a thin film(s) with intermediate transmittance or intermediatethickness. When using a slit pattern, it is preferable that the width ofthe slits or the distance between the slits is smaller than theresolution of a light exposer used for the photolithography. Anotherexample is to use reflowable photoresist. Once a photoresist patternmade of a reflowable material is formed by using a normal exposure maskonly with transparent areas and opaque areas, it is subject to reflowprocess to flow onto areas without the photoresist, thereby forming thinportions.

As a result, the manufacturing process is simplified by omitting aphotolithography step.

Many of the above-described features of the TFT array panel for an LCDshown in FIGS. 1 and 2 may be applicable to the TFT array panel shown inFIGS. 3-5.

An LCD according to another embodiment of the present invention will bedescribed in detail with reference to FIGS. 6, 7, 8 and 9.

FIG. 6 shows a layout view of a TFT array panel for an LCD according toanother embodiment of the present invention, FIG. 7 shows a layout viewof a common electrode panel for an LCD according to an embodiment of thepresent invention, FIG. 8 shows a sectional view of an LCD including theTFT array panel shown in FIG. 6 and the common electrode panel shown inFIG. 7, and FIG. 9 shows a sectional view of the LCD shown in FIG. 8taken along the line IX-IX′.

Referring to FIGS. 6-9, an LCD according to this embodiment alsoincludes a TFT array panel 100, a common electrode panel 200, a liquidcrystal (LC) layer 3 interposed between the TFT array and commonelectrode panels 100 and 200, and a pair of polarizers 12 and 22attached on outer surfaces of the TFT array and common electrode panels100 and 200.

The layered structure of the TFT array panel 100 according to thisembodiment is similar to those shown in FIGS. 1 and 2.

A plurality of gate lines 121 including gate electrodes 124 and gateline end portions 129 are formed on an insulating substrate 110, and agate insulating layer 140, a plurality of third, fourth and secondsemiconductor islands 151 a, 151 b and 154, and a plurality of ohmiccontact islands 161 a, 161 b, 163 and 165 are sequentially formedthereon. A plurality of data lines 171 including source electrodes 173and data line end portions 179 and a plurality of drain electrodes 175are formed on the ohmic contact islands 161 a, 161 b, 163 and 165 andthe gate insulating layer 140, and a passivation layer 180 is formedthereon. A plurality of first, second and third contact holes 181, 182and 185 are provided at the passivation layer 180 and the gateinsulating layer 140. A plurality of pixel electrodes 190 and aplurality of first and second contact assistants 81 and 82 are formed onthe passivation layer 180.

The TFT array panel according to this embodiment provides a plurality ofstorage electrode lines 131, which are separated from the gate lines121, on the same layer as the gate lines 121 without gate lineprojections. The storage electrode lines 131 are supplied with apredetermined voltage and each of the storage electrode lines 131includes a stem extending substantially parallel to the gate lines 121,a plurality of first, second, third and fourth storage electrodes 133 a,133 b, 133 c and 133 d branched from the stem, and a plurality ofstorage connections 133 e. Each of the storage electrode lines 131 isdisposed between two adjacent gate lines 121 and the stem is close to anupper one of the two adjacent gate lines 121.

The first and the second storage electrodes 133 a and 133 b extend in alongitudinal direction and face each other. The first storage electrodes133 a have a fixed end portion connected to the stem and a free endportion disposed opposite the fixed end portion and having a projection.The third and the four storage electrodes 133 c and 133 d obliquelyextend approximately from a center of the first storage electrodes 133 aand upper and lower ends of the second storage electrodes 133 b,respectively. Each of the storage connections 133 e is connected betweenadjacent first through fourth storage electrodes 133 a-133 d. However,the storage electrode lines 131 may have various shapes andarrangements.

A pixel electrode 190 overlaps a storage electrode line 131 includingfirst through fourth storage electrodes 133 a-133 d. Each pixelelectrode 190 is shaped approximately like a rectangle that having lowerand upper transverse main edges nearly parallel to the gate lines 121,left and right longitudinal main edges nearly parallel to the data lines171 and chamfered corners. The chamfered corners of the pixel electrode190 make an angle of about 45 degrees with the gate lines 121. The leftand right longitudinal main edges of the pixel electrode 190 aredisposed closer to a data line 171 than the first and second storageelectrodes 133 a and 133 b. The pixel electrode 190 with a drainelectrode 175 connected thereto, and the storage electrode line 131including the first through fourth storage electrodes 133 a-133 d form astorage capacitor.

The source electrodes 173 are spaced apart from the gate lines 121 andthe ohmic contacts 161 b are disposed between edges of the gateelectrodes 124 and the source electrodes 173. The third semiconductorislands 151 a and the ohmic contacts 161 a are disposed between the gatelines 121 and the data lines 171.

A plurality of isolated metal pieces 178 are formed on the gateinsulating layer 140, the passivation layer 180 and the gate insulatinglayer 140 that has a plurality of fixed end contact holes 183 a exposingportions of the storage electrode lines 131 near fixed end portions ofthe first storage electrodes 133 a, and a plurality of free end contactholes 183 b exposing free end portions of the first storage electrodes133 a, and a plurality of overpasses 83 are formed on the passivationlayer 180.

The isolated metal pieces 178 disposed on the gate lines 121 near thefirst storage electrodes 133 a, and the overpasses 83 are disposed onthe isolated metal pieces 178. The overpasses 83 cross over the gatelines 121 and are connected to exposed portions of the storage electrodelines 131 and exposed free end portions of the first storage electrodes133 a through the fixed end and free end contact holes 183 a and 183 b,respectively, which are disposed opposite each other with respect to thegate lines 121. The storage electrode lines 131 along with theoverpasses 83 can be used for repairing defects in the gate lines 121,the data lines 171, or TFTs.

Each pixel electrode 190 has a first center cutout 91, a first lowercutout 93 a, and a first upper cutout 93 b, which partition the pixelelectrode 190 into a plurality of partitions. The first center, firstlower and first upper pixel electrode cutouts 91, 93 a and 93 bsubstantially have an inversion symmetry with respect to an imaginarytransverse line bisecting the pixel electrode 190.

The first lower and first upper pixel electrode cutouts 93 a and 93 bobliquely extend from the right longitudinal main edge of the pixelelectrode 190 near right angles approximately to a center of the leftlongitudinal main edge of the pixel electrode 190 and overlap the thirdand the fourth storage electrodes 133 c and 133 d, respectively. Thefirst lower and first upper pixel electrode cutouts 93 a and 93 b aredisposed at lower and upper halves of the pixel electrode 190,respectively, which can be divided by the imaginary transverse line. Thefirst lower and first upper pixel electrode cutouts 93 a and 93 b makean angle of about 45 degrees to the gate lines 121, and extendsubstantially perpendicularly to each other.

The first center pixel electrode cutout 91 extends along the imaginarytransverse line and has an inlet from the right main edge of the pixelelectrode 190, which has a pair of inclined edges substantially parallelto the first lower cutout 93 a and the first upper cutout 93 b,respectively.

Accordingly, the lower half of the pixel electrode 190 is partitionedinto two lower partitions by the first lower pixel electrode cutout 93 aand the upper half of the pixel electrode 190 is also partitioned intotwo upper partitions by the first upper pixel electrode cutout 93 b. Thenumber of partitions or the number of pixel electrode cutouts variesdepending on the design factors such as the size of the pixels, theratio of the transverse main edges to the longitudinal main edges of thepixel electrode 190, and the type and characteristics of the LC layer 3.

The description of the common electrode panel 200 follows with referenceto FIGS. 7-9.

A light blocking member 220 referred to as a black matrix for preventinglight leakage is formed on an insulating substrate 210 such astransparent glass or plastic. The light blocking member 220 has aplurality of openings 225 that face the pixel electrodes 190 and it mayhave a substantially similar planar shape to the pixel electrodes 190.Otherwise, the light blocking member 220 may include a plurality ofrectilinear portions facing the data lines 171 on the TFT array panel100 and a plurality of widened portions facing the TFTs on the TFT arraypanel 100.

A plurality of color filters 230 is formed on the insulating substrate210 and is disposed substantially in the area enclosed by the lightblocking member 220. The color filters 230 may extend substantially in alongitudinal direction along the pixel electrodes 190. The color filters230 may represent one of the primary colors such as red, green or blue.

An overcoat 250 is formed on the color filters 230 and the lightblocking member 220. The overcoat 250 is preferably made of an organicinsulator. It prevents the color filters 230 from being exposed andprovides a flat surface. The overcoat 250 may be omitted.

A common electrode 270 is formed on the overcoat 250. The commonelectrode 270 is preferably made of transparent conductive material suchas ITO and IZO.

The common electrode 270 faces a pixel electrode 190 and includes afirst center cutout 71, a first lower cutout 73 a, and a first uppercutout 73 b. Each of the first center, first lower and first uppercommon electrode cutouts 71, 73 a and 73 b is disposed between adjacentfirst center, first lower and first upper pixel electrode cutouts 91, 93a and 93 b or between a first lower or first upper pixel electrodecutout 93 a or 93 b and a chamfered corner of the pixel electrode 190.Each of the first center, first lower and first upper common electrodecutouts 71, 73 a and 73 b has at least an oblique portion extendingsubstantially parallel to the first lower pixel electrode cutout 93 a orthe first upper pixel electrode cutout 93 b. The first center, firstlower and first upper common electrode cutouts 71, 73 a and 73 b havesubstantially an inversion symmetry with respect to the above-describedimaginary transverse line bisecting the pixel electrode 190.

Each of the first lower and first upper common electrode cutouts 73 aand 73 b includes an oblique portion, a transverse portion, and alongitudinal portion. The oblique portion extends approximately from theleft longitudinal main edge of the pixel electrode 190 approximately tothe lower or upper transverse main edge of the pixel electrode 190. Eachof the transverse and longitudinal portions extend from a respective endof the oblique portion along an edge of the pixel electrode 190,overlapping the edge of the pixel electrode 190, and making an obtuseangle with the oblique portion.

The first center common electrode cutout 71 includes a centraltransverse portion, a pair of oblique portions, and a pair of terminallongitudinal portions. The central transverse portion extendsapproximately from the left longitudinal main edge of the pixelelectrode 190 along the above-described transverse line. The obliqueportions extend from an end of the central transverse portionapproximately to the right longitudinal main edge of the pixel electrode190 and make oblique angles with the central transverse portion. Theterminal longitudinal portions extend from the ends of the respectiveoblique portions along the right longitudinal main edge of the pixelelectrode 190, overlapping the right longitudinal main edge of the pixelelectrode 190, and making obtuse angles with the respective obliqueportions.

The number of the first center, first lower and first upper commonelectrode cutouts 71, 73 a and 73 b may vary depending on the designfactors, and the light blocking member 220 may also overlap the firstcenter, first lower and first upper common electrode cutouts 71, 73 aand 73 b to block the light leakage through the first center, firstlower and first upper common electrode cutouts 71, 73 a and 73 b.

First and second alignment layers 11 and 21 that may be homeotropic arecoated on inner surfaces of the TFT array and common electrode panels100 and 200.

The pair of polarizers 12 and 22 are provided on outer surfaces of theTFT array and common electrode panels 100 and 200 so that theirpolarization axes may be crossed and one of the polarization axes may beparallel to the gate lines 121. When the angle between the polarizationaxes and the cutouts 71-72 b and 91-92 b is about 45 degrees, theefficiency of the light is very high. When the polarization axes issubstantially parallel to edges of the TFT array and common electrodepanels 100 and 200, i.e., parallel to the gate lines 121 and the datalines 171, the cost for the pair of polarizers 12 and 22 is small. Oneof the pair of polarizers 12 and 22 may be omitted when the LCD is areflective LCD.

The LCD may further include at least one retardation film (not shown)for compensating the retardation of the LC layer 3. The LCD may furtherinclude a backlight unit (not shown) supplying light to the LC layer 3through the pair of polarizers 12 and 22, the retardation film, and theTFT array and common electrode panels 100 and 200.

It is preferable that the LC layer 3 has negative dielectric anisotropyand it is subjected to a vertical alignment that LC molecules 31 in theLC layer 3 are aligned such that their long axes are substantiallyvertical to the surfaces of the TFT array and common electrode panels100 and 200 in the absence of an electric field. Accordingly, incidentlight cannot pass the crossed polarization system composed of the pairof polarizers 12 and 22.

Upon application of the common voltage to the common electrode 270 and adata voltage to a pixel electrode 190, an electric field substantiallyperpendicular to the surfaces of the TFT array and common electrodepanels 100 and 200 is generated. Both the pixel electrode 191 and thecommon electrode 270 are commonly referred to as “field generatingelectrodes.” The LC molecules 31 tend to change their orientations inresponse to the electric field such that their long axes areperpendicular to the field direction.

The first center, first lower and first upper pixel electrode cutouts91, 93 a and 93 b and the first center, first lower and first uppercommon electrode cutouts 71, 73 a and 73 b and the edges of the pixelelectrodes 190 distort the electric field to have a horizontal componentthat is substantially perpendicular to the edges of the first center,first lower and first upper pixel electrode cutouts 91, 93 a and 93 band the first center, first lower and first upper common electrodecutouts 71, 73 a and 73 b and the edges of the pixel electrodes 190.

Referring to FIG. 8, the first center, first lower and first uppercommon electrode cutouts 71, 73 a and 73 b and the first center, firstlower and first upper pixel electrode cutouts 91, 93 a and 93 b dividesa pixel electrode 190 into a plurality of sub-areas and each sub-areahas two primary edges making oblique angles with the main edges of thepixel electrode 190. Since most LC molecules 31 on each sub-area tiltperpendicular to the primary edges, the azimuthal distribution of thetilt directions are localized to four directions, thereby increasing thereference viewing angle of the LCD. The width of the sub-area ispreferably from about 12 microns to about 20 microns, and morepreferably from about 17 microns to about 19 microns.

The width of the first center, first lower and first upper commonelectrode cutouts 71, 73 a and 73 b and the first center, first lowerand first upper pixel electrode cutouts 91, 93 a and 93 b is preferablyequal to from about 9 microns to about 12 microns, and the shapes andthe arrangements of the first center, first lower and first upper commonelectrode cutouts 71, 73 a and 73 b and the first center, first lowerand first upper pixel electrode cutouts 91, 93 a and 93 b may bemodified.

At least one of the first center, first lower and first upper commonelectrode cutouts 71, 73 a and 73 b and the first center, first lowerand first upper pixel electrode cutouts 91, 93 a and 93 b can besubstituted with protrusions (not shown) or depressions (not shown)preferably having a width of from about 5 microns to about 10 microns.The protrusions are preferably made of organic or inorganic material anddisposed on or under the pixel electrode 190 or the common electrode270.

Many of the above-described features of the TFT array panel for an LCDshown in FIGS. 1 and 2 may be applicable to the TFT array panel shown inFIGS. 6-9.

An LCD according to another embodiment of the present invention will bedescribed in detail with reference to FIGS. 10, 11, 12 and 13.

FIG. 10 shows a layout view of a TFT array panel for an LCD according toanother embodiment of the present invention, FIG. 11 shows a layout viewof a common electrode panel for an LCD according to another embodimentof the present invention, FIG. 12 shows a sectional view of an LCDincluding the TFT array panel shown in FIG. 10 and the common electrodepanel shown in FIG. 11, and FIG. 13 shows a sectional view of the LCDshown in FIG. 12 taken along the line XIII-XIII′.

Referring to FIGS. 10-13, an LCD according to this embodiment alsoincludes a TFT array panel 100, a common electrode panel 200, an LClayer 3 interposed between the TFT array and common electrode panels 100and 200, and a pair of polarizers 12 and 22 attached on outer surfacesof the TFT array and common electrode panels 100 and 200.

Layered structures of the TFT array and common electrode panels 100 and200 according to this embodiment are similar to those shown in FIGS.6-9.

Regarding the TFT array panel 100, a plurality of gate lines 121including gate electrodes 124 and gate line end portions 129 and aplurality of storage electrode lines 131 are formed on an insulatingsubstrate 110. A gate insulating layer 140, a plurality of first andsecond semiconductor islands 151 and 154, and a plurality of ohmiccontacts 161, 163 and 165 are formed on the gate lines 121 and thestorage electrode lines 131. A plurality of data lines 171 includingsource electrodes 173 and data line end portions 179 and a plurality ofdrain electrodes 175 are formed on the ohmic contacts 163 and 165 andthe gate insulating layer 140, and a passivation layer 180 is formedthereon. A plurality of first, second and third contact holes 181, 182and 185 are provided at the passivation layer 180 and the gateinsulating layer 140. A plurality of pixel electrodes 190 includingfirst and second center and first through third lower and upper pixelelectrode cutouts 91-95 b and a plurality of first and second contactassistants 81 and 82 are formed on the passivation layer 180, and afirst alignment layer 11 is coated thereon.

Regarding the common electrode panel 200, a light blocking member 220, aplurality of color filters 230, an overcoat 250, a common electrode 270including first and second center and first through third lower andupper common electrode cutouts 71-75 b, and a second alignment layer 21are formed on an insulating substrate 210.

In this embodiment, each of the storage electrode lines 131 is nearlyequidistant from two adjacent gate lines 121 and includes a plurality offifth storage electrodes 135 expanding upward and downward. However, thestorage electrode lines 131 may have various shapes and arrangements.

Each of the drain electrodes 175 includes a wide end portion and twobranches. The wide end portion overlaps a fifth storage electrode 135and edges of the wide end portion are substantially parallel to edges ofthe fifth storage electrodes 135. The branches form a hook portionenclosing the gate electrode 124 and the branches are disposed on twoparallel straight lines. A source electrode 173 encloses end portions ofthe branches and has a shape like a character “S.”

This structure, having a rotational symmetry, also keeps the overlappingareas between the gate electrodes 124 and the drain electrodes 175uniform to maintain the parasitic capacitances between the gateelectrodes 124 and the drain electrodes 175 to be consistent.

The TFT array panel 100 according to this embodiment further includes ashielding electrode 88 disposed on the passivation layer 180. Theshielding electrode 88 is supplied with the common voltage and itincludes longitudinal portions extending along the data lines 171 andtransverse portions extending along the gate lines 121. The longitudinalportions fully cover the data lines 171, and the transverse portionsconnect adjacent longitudinal portions and lie within the boundary ofthe gate lines 121. The shielding electrode 88 blocks electric fieldsgenerated between the data lines 171 and the pixel electrodes 190 andbetween the data lines 171 and the common electrode 270 to reduce thedistortion of the voltage of the pixel electrode 190 and the signaldelay of the data voltages transmitted by the data lines 171. Sincethere is no electric field between the shielding electrode 88 and thecommon electrode 270, LC molecules (not shown) on the shieldingelectrode 88 remain in their initial orientations and thus the lightincident thereon is blocked. Accordingly, the shielding electrode 88 mayserve as a light blocking member.

Each of the center, first through third lower and first through thirdupper pixel electrode cutouts 71-74 b has at least one depressed notchat its oblique portion(s). The depressed notch(es) determine(s) the tiltdirections of the LC molecules on the center, first through third lowerand first through third upper common electrode cutouts 71-74 b and theymay be provided at the center, first through forth lower and firstthrough fourth upper pixel electrode cutouts 91-95 b.

Many of the above-described features of the TFT array panel for an LCDshown in FIGS. 6-9 may be applicable to the TFT array panel shown inFIGS. 10-13.

An LCD according to another embodiment of the present invention will bedescribed in detail with reference to FIGS. 14 and 15.

FIG. 14 shows a layout view of an LCD according to another embodiment ofthe present invention, and FIG. 15 shows a sectional view of the LCDshown in FIG. 12 taken along the line XV-XV′.

Referring to FIGS. 14 and 15, an LCD according to this embodiment alsoincludes a TFT array panel 100, a common electrode panel 200, an LClayer 3 interposed between the TFT array and common electrode panels 100and 200, and a pair of polarizers 12 and 22 attached on outer surfacesof the TFT array and common electrode panels 100 and 200.

Layered structures of the TFT array and common electrode panels 100 and200 according to this embodiment are similar to those shown in FIGS.10-13.

Regarding the TFT array panel 100, a plurality of gate lines 121including gate electrodes 124 and gate line end portions 129 and aplurality of storage electrode lines 131 including sixth storageelectrodes 137 are formed on an insulating substrate 110. A gateinsulating layer 140, a plurality of semiconductor stripes 152 includinga plurality of semiconductor stripe projections 153, and a plurality ofohmic contact stripes 161 including ohmic contact stripe projections 163and a plurality of ohmic contact islands 165 are sequentially formed onthe gate lines 121 and the storage electrode lines 131. A plurality ofdata lines 171 including source electrodes 173 and data line endportions 179 and a plurality of drain electrodes 175 are formed on theohmic contacts 163 and 165, and a passivation layer 180 is formedthereon. A plurality of first, second and third contact holes 181, 182and 185 are provided at the passivation layer 180 and the gateinsulating layer 140. A plurality of pixel electrodes 190 includingfirst and second center and first through third lower and upper pixelelectrode cutouts 91-95 b and a plurality of first and second contactassistants 81 and 82 are formed on the passivation layer 180, and afirst alignment layer 11 is coated thereon.

Regarding the common electrode panel 200, a light blocking member 220, aplurality of color filters 230, an overcoat 250, a common electrode 270including first and second center and first through third lower andupper common electrode cutouts 71-75 b, and a second alignment layer 21are formed on an insulating substrate 210.

In this embodiment, each of the source electrodes 173 has a shape like ascoop disposed over a gate electrode 124.

In addition, the semiconductor stripes 152 of the TFT array panel 100according to this embodiment have similar planar shapes as the datalines 171 and the drain electrodes 175 as well as the underlying ohmiccontacts 161 and 165. However, the semiconductor stripe projections 153of the semiconductor stripes 152 include some exposed portions, whichare not covered with the data lines 171 or the drain electrodes 175,such as portions located between the source electrodes 173 and the drainelectrodes 175.

As described above, the pixel electrodes and the contact holesconnecting the drain electrodes and the pixel electrodes are formedusing one lithography step. Accordingly, a lithography step for formingthe pixel electrodes is omitted to simplify the manufacturing method,thereby reducing the manufacturing time and cost.

An LCD according to another embodiment of the present invention will bedescribed in detail with reference to FIG. 16.

FIG. 16 is a layout view of an LCD according to another embodiment ofthe present invention.

Referring to FIG. 16, the layout structure of an LCD according to thisembodiment is similar to that shown in FIGS. 10-13.

In this embodiment, a pixel electrode 190 is divided into a lower pixelelectrode portion 190 a and an upper pixel electrode portion 190 bconnected to each other through a pixel electrode connection 90 ab. Thelower and upper pixel electrode portions 190 a and 190 b have firstthrough forth lower and upper pixel electrode cutouts 93 a-96 b thathave symmetry with respect to a center transverse line of the pixelelectrode 190.

A common electrode 270 has first through fifth lower and upper commonelectrode cutouts 73 a-77 b disposed between the first through forthlower and upper pixel electrode cutouts 93 a-96 b and the chamferedcorners of the pixel electrode 190.

Individual gate lines 121 are disposed between the lower pixel electrodeportions 190 a and the upper pixel electrode portions 190 b, and includea plurality of gate electrodes 124 projecting upwardly and downwardlyhaving symmetry with respect to the gate lines 121.

Individual storage electrode lines 131 are disposed between adjacentpixel electrodes 190 and include pairs of seventh storage electrodes 135a and 135 b overlapping the lower and upper pixel electrode portions 190a and 190 b.

Individual pairs of drain electrodes 175 a and 175 b overlap a gateelectrode 124 and have inversion symmetry with respect to a center lineof the gate lines 121. The pairs of drain electrodes 175 a and 175 binclude expansions overlapping the pairs of seventh storage electrodes135 a and 135 b.

Individual source electrodes 173 enclose a pair of drain electrodes 175a and 175 b having a shape like a character “H.”

The present invention can be employed to any display devices includingLCD and OLED display.

Although preferred embodiments of the present invention have beendescribed in detail hereinabove, it should be clearly understood thatmany variations and/or modifications of the basic inventive conceptsherein taught which may appear to those skilled in the present art willstill fall within the spirit and scope of the present invention, asdefined in the appended claims.

1. A thin film transistor array panel comprising: a gate electrode; asemiconductor layer; a gate insulating layer disposed between the gateelectrode and the semiconductor layer; a source electrode connected tothe semiconductor layer; and a drain electrode connected to thesemiconductor layer, spaced apart from the source electrode, andincluding two branches overlapping the gate electrode, wherein the twobranches of the drain electrode are spaced apart from each other and lieon a straight line or on two parallel straight lines.
 2. The thin filmtransistor array panel of claim 1, wherein the gate electrode has twoopposite edges meeting the two branches, respectively, and substantiallyparallel to each other.
 3. The thin film transistor array panel of claim1, further comprising: a gate line coupled to the gate electrode; a dataline coupled to the drain electrode; and a pixel electrode coupled tothe drain electrode.
 4. The thin film transistor array panel of claim 3,wherein the two branches have symmetry with respect to a center linepassing through the gate electrode and parallel to the gate line or thedata line.
 5. The thin film transistor array panel of claim 4, whereinthe source electrode encloses the two branches.
 6. The thin filmtransistor array panel of claim 5, wherein the source electrode hassymmetry with respect to the center line passing through the gateelectrode and parallel to the gate line or the data line.
 7. The thinfilm transistor array panel of claim 6, wherein the source electrode isspaced apart from the gate line except for the source electrode.
 8. Thethin film transistor array panel of claim 6, wherein the sourceelectrode has a shape like a character “H” or a shape like a character“H” rotated by about 90 degrees.
 9. The thin film transistor array panelof claim 8, wherein the pixel electrode includes a lower half and anupper half that are disposed opposite each other with respect to thegate line.
 10. The thin film transistor array panel of claim 9, whereinthe drain electrode has symmetry with respect to a center line of thegate line.
 11. The thin film transistor array panel of claim 1, furthercomprising a storage electrode line overlapping at least one of thepixel electrode and the drain electrode.
 12. The thin film transistorarray panel of claim 11, wherein the storage electrode is disposed nearan edge of the pixel electrode.
 13. The thin film transistor array panelof claim 11, wherein the storage electrode is disposed near an edge ofthe drain electrode.
 14. A thin film transistor comprising: a gateelectrode having a first edge and a second edge disposed opposite thefirst edge; a semiconductor layer; a gate insulating layer disposedbetween the gate electrode and the semiconductor layer; a sourceelectrode connected to the semiconductor layer; a drain electrodeconnected to the semiconductor layer, spaced apart from the sourceelectrode, and including a first branch and a second branch, wherein thefirst branch meets the first edge of the gate electrode at a onepredetermined angle, and the second branch meets the second edge of thegate electrode at the same or another predetermined angle.
 15. The thinfilm transistor of claim 14, wherein the first edge of the gateelectrode is substantially parallel to the second edge of the gateelectrode.
 16. A thin film transistor array panel comprising: a gateline including a gate electrode; a data line intersecting the gate lineand including a source electrode; a drain electrode disposed apart fromthe source electrode and including two branches; a semiconductor layerconnected to the source electrode and the drain electrode; a passivationlayer formed on the gate line, the data line, the drain electrode, andthe semiconductor layer; and a pixel electrode connected to the drainelectrode, wherein the source electrode includes two concave portionsconnected to each other and disposed opposite each other, and the twoconcave portions enclose respective branches of the drain electrode. 17.The thin film transistor of claim 16, wherein the source electrodecomprises a connecting portion connected between the concave portionsand the data line and the connecting portion is spaced apart from thegate line.
 18. The thin film transistor of claim 17, further comprisinga partitioning member partitioning the pixel electrode.
 19. The thinfilm transistor of claim 17, wherein the pixel electrode has a cutout.20. The thin film transistor of claim 18, wherein the pixel electrodehas a chamfered edge.